This class was created by Brainscape user Katrina Cuevas. Visit their profile to learn more about the creator.

Flashcard maker: Katrina Cuevas

Decks in this class (11)

The Fetch-Decode-Execute Cycle; including its effects on registers
The creator of this deck did not yet add a description for what is included in this deck.
4  cards
The use of pipelining in a processor to improve efficiency
The creator of this deck did not yet add a description for what is included in this deck.
5  cards
Von Neumann, Harvard and contemporary processor architecture
The creator of this deck did not yet add a description for what is included in this deck.
9  cards
The differences between and uses of CISC and RISC processors.
The creator of this deck did not yet add a description for what is included in this deck.
7  cards
Scheduling: round robin, first come first served, multi-level feedback queues, shortest job first and shortest remaining time
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19  cards
Translators: Interpreters, compilers and assemblers, stages of compilation (lexical analysis, syntax analysis, code generation and optimisation)
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18  cards
Assembly language (including following and writing simple programs with the Little Man Computer instruction set)
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11  cards
SQL – Interpret and modify
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12  cards
Transaction processing, ACID (Atomicity, Consistency, Isolation, Durability), record locking and redundancy
The creator of this deck did not yet add a description for what is included in this deck.
10  cards
The internet structure: The TCP/IP Stack
The creator of this deck did not yet add a description for what is included in this deck.
6  cards
How character sets (ASCII and UNICODE) are used to represent text
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4  cards

More about
OCR A level Computer Science - Paper 1 (2022)

  • Name Unspecified
  • Program type Unspecified
  • Course Unspecified
  • Instructor Unspecified
  • Standards Unspecified

The creator of this class did not yet add a description for what is included in this class.

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