This class was created by Brainscape user Katrina Cuevas. Visit their profile to learn more about the creator.

Decks in this class (11)

The Fetch-Decode-Execute Cycle; including its effects on registers
No deck description has yet been added by the author.
4  cards
The use of pipelining in a processor to improve efficiency
No deck description has yet been added by the author.
5  cards
Von Neumann, Harvard and contemporary processor architecture
No deck description has yet been added by the author.
9  cards
The differences between and uses of CISC and RISC processors.
No deck description has yet been added by the author.
7  cards
Scheduling: round robin, first come first served, multi-level feedback queues, shortest job first and shortest remaining time
No deck description has yet been added by the author.
19  cards
Translators: Interpreters, compilers and assemblers, stages of compilation (lexical analysis, syntax analysis, code generation and optimisation)
No deck description has yet been added by the author.
18  cards
Assembly language (including following and writing simple programs with the Little Man Computer instruction set)
No deck description has yet been added by the author.
11  cards
SQL – Interpret and modify
No deck description has yet been added by the author.
12  cards
Transaction processing, ACID (Atomicity, Consistency, Isolation, Durability), record locking and redundancy
No deck description has yet been added by the author.
10  cards
The internet structure: The TCP/IP Stack
No deck description has yet been added by the author.
6  cards
How character sets (ASCII and UNICODE) are used to represent text
No deck description has yet been added by the author.
4  cards

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ocr a level computer science - paper 1 (2022)

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