Microprocessors > ๐—–๐—ต๐—ฎ๐—ฝ๐˜๐—ฒ๐—ฟ ๐Ÿญ๐Ÿญ: Basic I/O Interface > Flashcards

๐—–๐—ต๐—ฎ๐—ฝ๐˜๐—ฒ๐—ฟ ๐Ÿญ๐Ÿญ: Basic I/O Interface Flashcards

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1
Q

o transfers information to an I/O device

A
  • OUT
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2
Q

o read information from an I/O device

A
  • IN
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3
Q

o 8-bit form (p8)

A
  • fixed address
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4
Q

o 16 bit I/O address

A
  • Variable address
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5
Q

o the I/O address

A
  • Port number
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6
Q
  • ISA
A

o industry standard architecture

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7
Q

o most common I/O transfer technique used in the Intel microprocessor-based system

A
  • isolated I/O
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8
Q

o does not use the IN, INS, OUT, or OUTS instructions

A
  • Memory-Mapped I/O
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9
Q

o uses any instruction that transfers data between the microprocessor and memory

A
  • Memory-Mapped I/O
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10
Q

o Three-state buffers are used to construct the 8-bit input port

A
  • Basic Input Interface
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11
Q

o receives data from the microprocessor and usually must hold it for some external device.

A
  • Basic Output Interface
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12
Q

o Also called polling

A
  • Handshaking
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13
Q

o synchronizes the I/O device with the microprocessor

A
  • Handshaking
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14
Q

o Are TTL and compatible, and therefore can be connected to the microprocessor and its interfacing components, or they are switch-based

A
  • Input Devices
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15
Q

o are far more diverse than input devices, but many are interfaced in a uniform manner

A
  • Output Devices
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16
Q

o programmable peripheral interface

A
  • PPI
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17
Q

o very popular, low-cost interfacing component found in many applications

A
  • PPI
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18
Q

o can interface any TTL-compatible I/O device to the microprocessor

A
  • 82C55
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19
Q

o have replaced LED displays in many applications

A
  • LCD
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20
Q

o a digital motor because it is moved in discrete steps as it traverses through 360ยฐ

A
  • stepper motor
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21
Q

o This allows external data to be stored into the port until the microprocessor is ready to retrieve it

A
  • Mode 1 Strobed Input
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22
Q

o loads data into the port latch, which holds the information until it is input to the microprocessor via the IN instruction

A
  • STB
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23
Q
  • STB
A

o Strobe

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24
Q

o an output indicating that the input latch contains information

A
  • IBF
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25
* IBF
o Input buffer full
26
o an output that requests an interrupt
o Interrupt request
27
* INTE
o interrupt enable
28
o is neither an input nor an output; it is an internal bit programmed via the port PC4 (port A) or PC2 (port B) bit position
* INTE
29
o The port C pins 7 and 6 are general-purpose I/O pins that are available for any purpose.
* PC7, PC6
30
o strobed input device
* Keyboard
31
o an output that goes low whenever data are output (OUT) to the port A or port B latch
* OBF
32
* OBF
o Output buffer full
33
o causes the pin to return to a logic 1 level. The signal is a response from an external device, indicating that it has received the data from the 82C55 port
* ACK
34
* ACK
o acknowledge signal
35
o a signal that often interrupts the microprocessor when the external device receives the data via the ACK signal.
* INTR
36
* INTR
o Interrupt request
37
o is neither an input nor an output; it is an internal bit programmed to enable or disable the INTR pin
* INTE
38
o strobe data into the printer
* DS
39
* DS
o Data strobe
40
o an output used to interrupt the microprocessor for both input and output conditions.
* INTR
41
o an output indicating that the output buffer contains data for the bidirectional bus
* OBF
42
o an input that enables the three-state buffers so that data can appear on port A
* ACK
43
o loads the port A input latch with external data from the bidirectional port A bus
* STB
44
o an output used to signal that the input buffer contains data for the external bidirectional bus
* IBF
45
o are internal bits (INTE1 and INTE2) that enable the INTR pin
* INTE
46
o These pins are general-purpose I/O pins in mode 2 controlled by the bit set and reset command
* PC0, PC1, PC2
47
* A0, A1
o Address inputs
48
o select one of four internal registers within the 8254
* A0, A1
49
the timing source for each of the internal counters
* CLK
50
o enables the 8254 for programming and reading or writing a counter
* CS
51
o controls the operation of the counter in some modes of operation
* G
52
* G
Gate
53
o connects to the system ground bus
* GND
54
o counter output
* OUT
55
o where the waveform generated by the timer is available
* OUT
56
o causes data to be read from the 8254 and often connects to the IORC signal
* RD
57
* RD
o Read
58
o Connects to the +5.0V power supply
* Vcc
59
o causes data to be written to the 8254 and often connects to the write strobe IOWC
* WR
60
o Allows the 8254 counter to be used as an events counter
* MODE 0
61
o Causes the counter to function as a retriggerable, monostable multivibrator
* MODE 1
62
o Allows the counter to generate a series of continuous pulses that are one clock pulse wide
* MODE 2
63
o Generates a continuous square wave at the OUT connection, provided that the G pin is a logic 1
* MODE 3
64
o Allows the counter to produce a single pulse at the output
* MODE 4
65
o A hardware triggered one-shot that functions as mode 4, except that it is started by a trigger pulse on the G pin instead of by software
* MODE 5
66
o programmable communications interface designed to connect to virtually any type of serial interface
* PC16550D
67
o transmitted and received without a clock or timing signal
* Asynchronous Serial Data
68
PLCC
o Plastic leadless chip carrier
69
FM
o Frequency modulation
70
CB
o Citizens band
71
o address inputs are used to select an internal register for programming and also data transfer
* A0, A1, A2
72
* ADS
o Address strobe
73
o used to latch the address lines and chip select lines
* ADS
74
o where the clock signal generated by the baud rate generator from the transmitter section is made available
* BAUDOUT
75
o must all be active to enable the 16550 UART
* CS0, CS1, CS2
76
o indicates that the modem or data set is ready to exchange information
* CTS
77
* CTS
o Clear to send
78
o received data contain the wrong parity
* parity error
79
o start and stop bits are not in their proper places
* framing error
80
o data have overrun internal receiver FIFO buffer
* overrun error
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