Chapter 1 - Processor components

Question 1

Control unit

Answer 1

• Controls and coordinates activities of the CPU
• In charge of FDE cycle

Question 2

Buses

Answer 2

• set of parallel wires connecting two or more components
• consists of 8, 16, 32 or 64 lines
• control and data buses are bi-directional (signals can be carried both ways)
• shared transmission medium, so only one device can transmit at any one time

Question 3

Buses - Control bus

Answer 3

Ensures that access to and use of data and address buses does not lead to conflict; transmits command, timing and specific status information e.g.
- Memory write – data on the data bus is written into the addressed location
- Memory read – data from addressed location is read
- Clock – used to synchronise operations

Question 4

Buses - Data bus

Answer 4

Provides path for moving data and instructions; largest operand possible is determined by the width of the data bus

Question 5

Buses - Address bus

Answer 5

Transmits memory addresses of words, so that data can be retrieved; width of address bus determines the maximum possible memory capacity
- Words – a fixed size group of digits which memory is divided into; different types of processors have different word sizes; each has a specific memory address

Question 6

ALU

Answer 6

Performs arithmetic and logical operations on data e.g. add, multiply, shift operations and boolean logic operations
- it is a type of register

Question 7

Registers

Answer 7

Special memory cells that operate at very high speeds
There 16 general-purpose registers, but the accumulator (holds result of operation) takes the place all of them for simplicity

Question 8

Registers - PC

Answer 8

Holds address of next instruction to be executed; could jump to another instruction/not go in a sequence

Question 9

Registers - CIR

Answer 9

Holds current instruction being executed

Question 10

Registers - MAR

Answer 10

Holds the address of the memory location from which data/instructions need to be fetched or written to

Question 11

Registers - MDR

Answer 11

Used to temporarily store data from or to be written to memory

Question 12

FDE cycle - Fetch

Answer 12

1. Address of next instruction is copied from PC to MAR.
2. Instruction held at that address is copied to MDR. Content of PC is incremented to hold the address of next instruction.
3. Contents of MDR are copied to CIR

Question 13

FDE cycle - Decode

Answer 13

4. Instruction held in CIR is decoded. It is split into opcode (determines type of instruction in assembly language e.g. SUB, LDA, ADD) and operand (data to be operated one), holding either:
   - Address of data to be used is copied to MAR
   - Actual data is copied to MDR
   - data passed in to ALU/ACC

Question 14

FDE cycle - Execute

Answer 14

5. Appropriate instruction/opcode is carried out on the operand.

Question 15

Registers - ACC

Answer 15

Temporarily holds result of arithmetic or logic operation