Module 4: Sequential Logic

Question 1

RS-Latch

Answer 1

bistable circuit (meaning it can happily exist in either of two states) with the ability to “store” its last output

Called a latch because it can latch onto incoming data

Question 2

D-Latch

Answer 2

enables input on a gated S-R Latch a way to latch the Q and NOT Q outputs without regard to the status of S or R, we can eliminate one of those inputs to create a multivibrator latch circuit with no “illegal” input states

Question 3

Timing Diagram

Answer 3

a type of truth table for sequential logic gates

Question 4

Clock

Answer 4

acts as the heartbeat of our system, creating “windows” to synchronize information windows across our CPU

Question 5

D flip flop (DFF)

Answer 5

an “edge-triggered” device that stores data at the edge of the clock. the DFF takes a clock input (often denoted with a triangle)

Question 6

Latch vs. Flip Flop

Answer 6

latch is “level” sensitive; FF is “edge” sensitive

Question 7

Registers

Answer 7

collection of latches or flip-flops controlled by a common WE or CLK

Question 8

Finite State Machine

Answer 8

Computation model that can be implemented with hardware or software and used to simulate sequential logic and some computer programs; sometimes called a “finite-state automaton”

Question 9

computer memory

Answer 9

physical devices capable of storing information temporarily like RAM or permanently like ROM

Question 10

RAM

Answer 10

by specifying address, one can read or write to any “drawer” in the memory at random

Question 11

ROM

Answer 11

non volatile memory used in computers and other electronic devices to store data permanently; typically used to hold a small program or setting that a computer might rely on for startup

Question 12

From latches to flip flops

Answer 12

for a d-latch, windows of time to store/read information are equal:

• when the WE is 1, d-latch is open, Q follows D
• when the WE is 0, d-latch is closed, data is stored and read-only
• we prepare what we wish to store right before the latch closes

for a DFF, the window of time for writing is shorter but we have more time to read:

• we can only store data in the DFF when the clock transitions from 0 to 1 (note: negative edge FFs also exist)
• otherwise, the dff is closed and we can only read from it
• we prepare what we wish to store right before the positive edge of the clock

Question 13

Clock frequency and period

Answer 13

• the number of cycles per second is the clock frequency measured in cycles per second or “Hertz (Hz)”
• the clock period refers to the duration of one clock cycle; the period and frequency are inversely related
• example clock frequency: 2.5 GHz = 2.5 x 10^9 Hz
• –corresponding clock period = 1/(2.5 x 10^9) - .4 x 10-9 seco
• –or 4 nanoseconds

Question 14

Finite State Machine (FSM)

Answer 14

• a machine that can be build using combinational and sequential logic
• the machine can only be in a finite number of states
• a CPU is a complicated example of an FSM
• –a toaster is an example of an FSM with two basic states (off and on)
• –most electronic machines are examples of FSMs
• FSMs consist of 3 basic parts:
• -an n-bit register which stores the state of the machine
• -a block of logic that computes the next state as a function of the current state and any inputs
• -a block of logic that computes the output based on the current state

Question 15

RAM

Answer 15

Static RAM (SRAM): 6 transistors per bit
–fast
–maintains the data as long as power is applied
Dynamic Ram (DRAM): 1 transistor per bit
–denser but slower
–relies of “capacitance” to store data
–needs constant refreshing of data to hold charge on capacitor

Question 16

Hierarchy of Memory in Computer

Answer 16

1. CPU
2. CACHE
3. Main Memory
4. Disks (permanent storage)