SR flip flop circuit and truth table
Uses 2 nand gates the outputs feeding back into the other gate
First output is Q, second output is not Q
First input S, second input R
input 0 0 is unusable state
whatever the inputs are the corresponding output is the opposite
input 1 1 is remembered state and the outputs will be the same as before
How does a D type flip flop work and the versions for up counter and down counter
Active high clock (triggers on rising edge) D pin gets copied to Q and not Q has the opposite
D and not Q are connected because you want the output to change every clock pulse
Q is the output and connects to any LEDs
Down counter
Q connects to the clock(the wires are going down ie down counter)
So on the very first clock pulse the outputs of every counter goes high and so you start with all the bit high. Next bit gets triggered by a rising edge of Q
UP counter (the weird one)
Not Q connects to the clock
next bit get triggered by the falling edge of Q
