What is a flip‑flop?
An edge‑triggered memory element that stores 1 bit of data.
How do flip‑flops differ from latches?
Flip‑flops are edge‑triggered
What triggers a flip‑flop?
A clock edge (rising or falling).
What is the purpose of the clock input?
Synchronises state changes across a digital system.
What is the output of a flip‑flop?
Q and Q̅ (complementary outputs).
What is the basic SR flip‑flop problem?
S = 1 and R = 1 is an invalid state.
What does the D flip‑flop eliminate?
The invalid SR condition by ensuring S = D and R = D̅.
What is the characteristic equation of a D flip‑flop?
Q(next) = D.
When does a D flip‑flop update?
Only on the active clock edge.
What is the purpose of a D flip‑flop?
Data storage, registers, synchronisation.
What is the JK flip‑flop?
A flip‑flop that eliminates the SR invalid state and allows toggling.
What is the characteristic equation of a JK flip‑flop?
Q(next) = JQ̅ + K̅Q.
What happens in a JK flip‑flop when J = 0 and K = 0?
No change.
What happens when J = 1 and K = 0?
Q is set to 1.
What happens when J = 0 and K = 1?
Q is reset to 0.
What happens when J = 1 and K = 1?
The flip‑flop toggles.
What is the T flip‑flop?
A toggle flip‑flop derived from JK with J = K = T.
What is the characteristic equation of a T flip‑flop?
Q(next) = Q̅ when T = 1, else Q(next) = Q.
What is the purpose of a T flip‑flop?
Frequency division and counters.
What is edge‑triggering?
The flip‑flop responds only at the instant of a clock edge.
What is a rising‑edge trigger?
Flip‑flop updates on the 0→1 transition.
What is a falling‑edge trigger?
Flip‑flop updates on the 1→0 transition.
What is setup time?
Minimum time D must be stable BEFORE the clock edge.
What is hold time?
Minimum time D must remain stable AFTER the clock edge.
